The advent of the digital age established, and continues to create, advancements over analog design in such technological categories as computing, communications, and electronic recreation. Access to these technologies, therefore, is becoming increasingly affordable and realizable through digital innovation.
The digital age, however, has not obviated the need for analog circuitry. Consequently, both Analog to Digital Conversion (ADC) and Digital to Analog Conversion (DAC) technologies are very much in demand in order to bridge the gap between the analog and digital worlds.
DAC technologies are required, for example, when digital information is required to control an analog component. Accordingly, control loops often incorporate digital computation circuitry to compare a reference signal with a generated signal in order to calculate a digital error between the two signals. Often, the digital error signal is then applied to an analog correction component, such as a Voltage Controlled Oscillator (VCO) or a Current Controlled Attenuator (CCA), to correct the error. As such, a DAC is then required to convert the digital error signal into an analog form suitable for use by the analog correction component.
Generally speaking, digital to analog conversion is accomplished through the scaling, e.g., division or multiplication, of a reference signal, e.g., voltage, current or charge, into quantized signal segments. Each segment may then be combined in response to an applied input code to form the analog output signal. For an ideal DAC, stepping the input code from all logic zero values to all logic one values renders a rising (or falling) analog staircase waveform having equal magnitude steps. Once the ideal staircase waveform function is smoothed, it forms a perfectly straight line. Each step of the staircase waveform represents a Least Significant Bit (LSB) having a magnitude equal to: LSB=FSR/(2N−1), where FSR is the Full Scale Range of the DAC output signal and N is resolution of the DAC in bits.
For a non-ideal DAC, however, Differential Non-Linearities (DNL) and Integral Non-Linearities (INL) perturb the staircase waveform and thus adversely affect the linearity of the DAC. DNL, for example, affects the magnitude of each step, while INL affects the straightness of the staircase waveform when smoothed. Both parameters, therefore, contribute to the inaccuracy of the static code conversion and influence the quality of the dynamic analog output.
While design constraints for the DNL specification may be architecturally relaxed by employing thermometer or segmented structures, the INL specification is fundamentally coupled to the static errors of the analog components that generate the output signal. In order to counteract the static errors, two conventional approaches have been employed. First, an intrinsic DAC design approach is used, which employs large analog devices to reduce the static error to acceptable levels. Alternatively, a calibrated design approach is used, which employs additional calibration logic and operations to improve the linearity.
The calibrated design approach also employs two main techniques for improving linearity. The first technique employs a single parallel CALibrating DAC (CALDAC) to correct the analog output value for each particular input code used. Synchronization problems, however, adversely affect this approach, especially at high speeds.
With the second technique, calibration is instead applied to each individual analog element that is used to produce the output signal, through the use of individual CALDACs, or biasing capacitors. Such calibration schemes use components that sense a difference between a reference and a calibrated element, such as through the use of a single-bit ADC (a comparator) or a multi-bit ADC. However, these components may cause problems due to their substantially unavoidable input offsets.
Conventional input offset cancellation techniques are then employed, whereby the signal being calibrated and the reference signal are applied to the inputs of an ADC during a first measurement. The inputs are then swapped, a second measurement is taken, and a mean value is calculated from the first and second measurements. Such a cancellation approach, however, places stringent accuracy requirements on both the measurement components and the calibrating elements.